Signal Integrity Course

This course is for electrical engineers who are new to tscircuit. It takes you from a voltage divider to an eye diagram on a routed DDR3 trace. Each lesson adds one new idea and ends with a check you can do on paper.

You don't need to know React. A tscircuit file is a function that returns your circuit as tags. <resistor> is a resistor, <trace> is a connection, and tsci simulate runs the analysis you declare.

Route

Part 1 · Simple: schematic circuits

Engine: ngspice. Traces are ideal wires.

#	Lesson	You learn	Check by hand
1	Voltage divider	Sources, probes, DC operating point, reading the output	Vout = V·R2/(R1+R2)
2	Diode I–V curve	DC sweep	Knee near 0.6–0.7 V
3	RC step response	Transient analysis	63 % at τ = RC
4	RC Bode plot	AC sweep	−3 dB at fc = 1/(2πRC)
5	Parameter sweeps	analog.sweepparameter	τ scales with R
6	Real circuits	Rectifiers, switches, converters	Datasheet behaviour

Part 2 · Medium: the trace is real

#	Lesson	You learn	Check by hand
7	A trace is an RLC	Fast edges ring on a lumped trace	f ≈ 1/(2π√LC)
8	Transmission line	Z0, delay, reflections	Open end doubles the step
9	Termination	Series vs parallel termination	Clean when R = Z0
10	Your first pcb_spice run	The board supplies the R, L and C	Microstrip Z0 formula
11	Bits and eyes	Bit patterns, UI, eye diagrams, ISI	Eye closes once a round trip exceeds a bit
12	Real buffers (IBIS)	<ibismodel>, drive strength	Best drive ≈ Z0, not the strongest
13	The return path	Plane distance sets L and Z0	L grows with distance to the plane
14	Changing layers	Vias and stubs	A dip at the via
15	Crosstalk	Several lanes, aggressor vs victim, sanity-checking a model	Should fall with spacing

Part 3 · Hard: DDR3 on the AM3352 board

#	Lesson	You learn
16	One DQ lane	Simulate the real board, find routed pins, vendor IBIS models, the DQ0 eye
17	Add the strobe	DQS/DQSn, centre-aligned writes, quiet vs switching
18	Corners and settings	IBIS corners, drive strength, ODT
19	The full byte lane	Eight DQ bits, DM and DQS with coupling, worst bit
20	Routed copper	Real curves, planes and vias
21	Timing check	Setup/hold, VREF thresholds, reads
22	Power	VDDQ impedance, simultaneous switching noise

Lesson status

Each lesson starts with a status badge:

• ✅ Runs today. We ran the code with tsci simulate, and the numbers on the page come from that run.
• 🟡 Not run yet. The code uses elements tscircuit already has, but nobody has run this exact example yet. Expect to adjust it.
• 🚧 Not supported yet. This is the setup we're aiming for. The page says what's missing today.

How every lesson is laid out

1. Goal: one sentence.
2. Build: one *.circuit.tsx file.
3. Run: bunx tsci simulate <file>.
4. What you see: the real output.
5. Check by hand: the paper calculation it should match.
6. Try this: one change to make on your own.

Example files

Every runnable lesson has a file in tutorial/course of the AM3352 repo. That folder also has the synthetic teaching IBIS model used in Part 2. Clone the repo and run them from its root.

Before you start

bun install -g tscircuit     # or use bunx tsci in a project
brew install ngspice         # Part 1 onwards
# Part 2 onwards (pcb_spice): fasthenry and FasterCap on your PATH

Reading tsci simulate output

The ngspice engine prints a table. Columns are node voltages (v(n1), v(n2), …) and source currents, not your probe names. In a small circuit, find your node by its value. Lesson 1 shows how.