7 · A trace is an RLC

Status: ✅ Runs today

Goal: see why a trace stops being a wire once edges get fast.

A 10 cm trace over a ground plane has roughly 300 nH/m and 100 pF/m, so about 30 nH and 10 pF in total. In this lesson you put those values in the schematic by hand.

Build

07-trace-rlc.circuit.tsx

import { analog } from "tscircuit"

// 10 Ω driver, 1 ns edge, 10 cm trace lumped as 30 nH + 10 pF.
export default () => (
  <board routingDisabled>
    <voltagesource name="V1" waveShape="square" voltage="3.3V" frequency="10MHz"
      dutyCycle={0.5} riseTime="1ns" fallTime="1ns" />
    <resistor name="RS" resistance="10" footprint="0402" />
    <inductor name="LT" inductance="30nH" footprint="0402" />
    <capacitor name="CT" capacitance="10pF" footprint="0402" />
    <trace from=".V1 > .pin1" to=".RS > .pin1" />
    <trace from=".RS > .pin2" to=".LT > .pin1" />
    <trace from=".LT > .pin2" to=".CT > .pin1" />
    <trace from=".CT > .pin2" to=".V1 > .pin2" />
    <voltageprobe name="V_RX" connectsTo=".CT > .pin1" referenceTo=".V1 > .pin2" />
    <analog.transientsimulation name="TRACE_RING" spiceEngine="ngspice"
      duration="60ns" timePerStep="0.05ns" />
  </board>
)

Run

bunx tsci simulate 07-trace-rlc.circuit.tsx

What you see

At the receiver (the capacitor node), the rising edge overshoots and then rings down:

Peak	Time	Voltage
1	3.08 ns	3.64 V
2	6.53 ns	3.49 V
3	9.98 ns	3.41 V
4	13.43 ns	3.36 V

Check by hand

• Ring frequency: f = 1 / (2π√(30 nH × 10 pF)) = 290 MHz, a period of 3.45 ns. The peaks in the sim are 3.45 ns apart ✓
• Damping: ζ = (R/2)·√(C/L) = 5 × √(10p/30n) = 0.091. Each peak's overshoot is about 0.56× the one before, and e^(−2πζ) ≈ 0.56 ✓

Try this

Make the driver slower (riseTime="5ns"). Once the edge is slower than the ring period, the overshoot almost disappears. The edge rate sets whether a trace matters, not the clock frequency.